Researcher in low power and asynchronous circuits, Newcastle University.
MEng EEE, University of Southampton 2016.
Self-timed inference datapath based on the Tsetlin Machine algorithm.
A presentation at the SCONA workshop, DATE 2020.
A fresh ideas paper presented at ASYNC 2019.
Adder and comparator designs with improved latency and energy compared to synchronous versions. The comparator benefits especially from dual-rail logic.
Self-timed circuits can provide better performance with lower design cost.
Best poster award at PATMOS 2017.
Energy harvester, battery charger and power controller for satellite subsystems. Part of my Masters group project.
A small PCB design housing three LEDs. A linear current source saves PCB space, and a potentiometer sets the brightness.
A simple thermocouple meter using a PIC microcontroller and 16x2 character LCD.
Custom built water loop with DIY reservoir side-panel.
Convert Synopsys Liberty fomat to SIS Genlib.
Lock screen displaying how long the user has been away.
Collection of useful TeX packages for EEE.
A minimal vimrc with no plugins.