Researcher in low power and asynchronous circuits, Newcastle University.
MEng EEE, University of Southampton 2016.

Research

Sustainable, Pervasive AI

A 3-minute PhD Pitch presented at UKCAS 2020.

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Sustainable, Pervasive AI

A. Wheeldon “Sustainable, Pervasive AI”, UKCAS 2020.

Learning automata based energy-efficient AI hardware design for IoT applications

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Learning automata based energy-efficient AI hardware design for IoT applications

A. Wheeldon, R. Shafik, T. Rahman, J. Lei, A. Yakovlev, O-C. Granmo, “Learning automata based energy-efficient AI hardware design for IoT applications,” Philos. Trans. R. Soc. A Math. Phys. Eng. Sci., vol. 378, no. 2182, Oct 2020.

Low-Latency Asynchronous Logic Design for Inference at the Edge

Self-timed inference datapath based on the Tsetlin Machine algorithm.

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Low-Latency Asynchronous Logic Design for Inference at the Edge

A. Wheeldon, A. Yakovlev, R. Shafik, J. Morris, “Low-Latency Asynchronous Logic Design for Inference at the Edge”, arXiv:2012.03402 [cs, eess], Dec 2020.

Tsetlin Machine: A new Paradigm for Pervasive AI

A presentation at the SCONA workshop, DATE 2020.

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Tsetlin Machine: A new Paradigm for Pervasive AI

A. Wheeldon “Tsetlin Machine: A new Paradigm for Pervasive AI”, SCONA Workshop, DATE 2020.

Variable Bitwidth Asynchronous Dot Product

A fresh ideas paper presented at ASYNC 2019.

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Variable Bitwidth Asynchronous Dot Product

J. Edwards, A. Wheeldon, R. Shafik, A. Yakovlev, “A Variable Bitwidth Asynchronous Dot Product Unit”, ASYNC 2019 Fresh Ideas.

Self-timed, Minimum Latency Circuits for IoT

Adder and comparator designs with improved latency and energy compared to synchronous versions. The comparator benefits especially from dual-rail logic.

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Self-timed, Minimum Latency Circuits for IoT

A. Wheeldon, J. Morris, D. Sokolov, and A. Yakovlev, “Self-timed, minimum latency circuits for the Internet of Things,” in Integration, the VLSI Journal, Jan 2019.

DOI

Faster and Cheaper Circuits through Self-timing

Self-timed circuits can provide better performance with lower design cost.

Power Proportionality Poster

Best poster award at PATMOS 2017.

Power Proportional Adder Design

A self-timed adder optimised for subthreshold shows power proportionality.

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Power Proportional Adder Design

A. Wheeldon, J. Morris, D. Sokolov, and A. Yakovlev, “Power proportional adder design for Internet of Things in a 65 nm process,” in 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2017, pp. 1–6.

DOI