Researcher in low power and asynchronous circuits, Newcastle University.
MEng EEE, University of Southampton 2016.
Research
Low-Latency Asynchronous Logic Design for Inference at the Edge
Self-timed inference datapath based on the Tsetlin Machine algorithm.
Tsetlin Machine: A new Paradigm for Pervasive AI
A presentation at the SCONA workshop, DATE 2020.
Self-timed, Minimum Latency Circuits for IoT
Adder and comparator designs with improved latency and energy compared to synchronous versions. The comparator benefits especially from dual-rail logic.
Faster and Cheaper Circuits through Self-timing
Self-timed circuits can provide better performance with lower design cost.
Power Proportional Adder Design
A self-timed adder optimised for subthreshold shows power proportionality.
Hardware
Satellite Power Supply
Energy harvester, battery charger and power controller for satellite subsystems. Part of my Masters group project.
Compact LED Lighting
A small PCB design housing three LEDs. A linear current source saves PCB space, and a potentiometer sets the brightness.
Software
liberty-to-genlib
i3lock-awaytimer
texmf
vimrc-bare
- Researcher in low power, asynchronous circuits.
-
contact@awheeldon.com
i3lock-awaytimer
texmf
vimrc-bare
- Researcher in low power, asynchronous circuits.
-
contact@awheeldon.com
texmf
vimrc-bare
- Researcher in low power, asynchronous circuits.
-
contact@awheeldon.com
vimrc-bare
- Researcher in low power, asynchronous circuits.
-
contact@awheeldon.com
- Researcher in low power, asynchronous circuits.
- contact@awheeldon.com